Integrated circuit test arrangement and method for maximizing the use of tester comparator circuitry to economically test wide data I/O memory devices

ABSTRACT

A device tester provides signals to a device under test. A parallel compare circuit then receives all the outputs of the device and compares each of the outputs with one another simultaneously. Next the parallel compare circuit will produce an output pattern which is compared to the expected test pattern stored in the tester. If the output pattern from the parallel compare circuit is the same as the expected test pattern the device will be considered a properly working device; conversely, if the patterns do not match the device will be considered an improperly working device.

This application is a continuation of application Ser. No. 07/979,994,filed Nov. 23, 1992, now abandoned.

FIELD OF THE INVENTION

This invention relates generally to testing integrated circuit devicesand more specifically to an apparatus and method of testing memorydevices.

BACKGROUND OF THE INVENTION

A memory tester performs a test on memory devices by supplying asequence of addresses and data patterns to the device under test (DUT),by reading the output from the DUT consisting of a series of testsignals which create a test signal pattern and thereby determining ifthe DUT passed or failed the test. The output pin of the DUT is coupledto the receiver circuitry of the device tester which compares the testsignal pattern on the output pin of the DUT with a reference test signalpattern stored within the tester to determine whether the DUT passed orfailed the test.

Memory devices are available with various configurations and variousnumbers of outputs. For example, the one megabit dynamic random accessmemory (1M DRAM) device TMS4C1024 manufactured by Texas Instruments hasa one megabit by one data I/O pin configuration, while the 1M DRAMTMS44C256 also manufactured by Texas Instruments has a 256 kilobit byfour data I/O pins (256K×4) configuration. Even though the configurationand number of data I/O pins of these two devices is dissimilar, both ofthese devices are 1 MB DRAM devices.

For example, a memory tester may have four transceiver circuits andrequires the connection of a separate transceiver circuit to each memorydevice data input/output pin to perform a device test. Therefore, onetester transceiver circuit is required to test a memory device havingthe 1M×1 configuration. A total of four memory devices in the 1M×1configuration can be tested at once on this device tester which containsfour transceiver circuits. Comparatively, testing a 1 MB DRAM in the256K×4 configuration requires the use of four tester transceivercircuits per memory device, which therefore occupies the entire tester.In summary, because this device tester has only four receiver circuits,four 1M×1 configuration devices or only one 256K×4 configuration devicecan be tested at once. As a result, the number of devices a tester cantest in parallel decreases with increasing number of data input/outputpins on each device.

Using current tester design methodologies, many testers are incapable ofeconomically testing wide I/O devices. The cost of redesigning a testerto add more receivers is cost prohibitive as receivers are complex andtherefore very expensive. Tester manufacturers invest one to two yearsof design effort to double a particular tester's throughput capabilitythrough redesigning the memory algorithm generator.

There is a problem in finding a way to economically test wide data I/Omemory devices.

SUMMARY OF THE INVENTION

These problems are solved by a method for testing semiconductor deviceswhere the number of data I/O's coupled to device tester transceivers isreduced. In general, the invention includes a parallel compare circuitwhich takes all the outputs of a device and compares each of the outputswith one another simultaneously. If all of the outputs are of the samepattern state, the parallel compare circuit will produce an outputpattern which is the same as the reference pattern generated by atester. The result is that the device will pass the test and later besold. If one or more of the outputs is incorrect, the parallel comparecircuit will produce an output pattern that is not the same as thereference pattern generated by a tester. The result is that the devicewill fail the test and later be repaired or discarded.

Some of the advantages of the invention are 1) it converts a testerincapable of testing devices with numerous data I/0 pins to a testerwhich can test such devices, 2) tester capability and useful life isincreased at low cost, 3) design time for doubling tester capacity canbe reduced by half, and 4) the number of devices which can be tested inparallel is increased.

BRIEF DESCRIPTION OF THE DRAWING

A better understanding of the invention will be gained by reading thefollowing specification with reference to the drawing herein:

FIG. 1 is a block diagram illustrating a test system including a devicetester coupled to a four data terminal device under test and a parallelcompare circuit of the preferred embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1 is a block level diagram illustrating a test system 10 having atypical device tester 30 coupled to a device under test (DUT) 31. Thepreferred embodiment of the invention operates within this system. Thedevice tester 30 sends control signals as well as data to the DUT 31. Inresponse, the DUT 31 sends output data signals to the device tester 30.

A typical device tester 30 used to test a 1 MB DRAM, such as theTMS44C256 manufactured by Texas Instruments Incorporated, uses controlsignals on leads 32-36 and input and output data signals on one lead 45from one of four transceivers 41-44.

First of all, to write data the device tester 30 sends address signalsto the device under test 31 via the address bus (ADR) which includesnine leads 36. A write enable (WE) signal on control lead 35 enablesdata to be written to the DUT 31. The row address strobe (RAS) signal oncontrol lead 32 strobes in the row address on address bus leads 36 intothe device under test. Address bus (ADR) includes nine leads 36. Thus,nine row address bits are set up on pins A0 through A8 and latched ontothe DUT 31. The column address strobe signal (CAS) on the lead 33strobes in the column address also on address leads 36. Thus, ninecolumn address bits are set up on pins A0 through A8 and latched ontothe DUT 31.

After the device tester 30 sends the address signal to the device undertest 31 as described above, the device tester 30 sends a test datasignal to parallel compare circuit 91. The test data signal that is sentto the device under test 31 is also stored by control circuitry 90 inthe store register 92 of the device tester 30. In the next step the testdata signal in the parallel compare circuitry is duplicated by enablingmultiple paths through the parallel compare circuitry by enablingtransistors 80-83. The duplicated test data signals are stored in thedevice under test 31 in plural storage locations selected by therespective row and column address signal on line 36.

The parallel compare circuit 91 includes one or more gating transistors80-83 responsive to a write enable signal on the lead 35 from thecontrol circuitry 90 for coupling the transceiver circuit 41 to thedevice under test 31 when data is sent to the device under test 31. Datain/data out lines 37-40 duplicates the test data signal from the testerduring a write operation.

The output enable (OE) signal on control lead 34 activates the deviceoutput during a read operation. During a read operation the deviceoutput data signals are sent on lines 37-40 to the tester. The deviceunder test 31 re-addresses the plural storage locations, and reads outthe stored duplicated test data signals from the plural storagelocations to the parallel compare circuitry 91 in response to a readsignal on the control lead 34. The control signal disables thetransistors 80-83 causing the stored duplicated test signals read out ofdevice under test 31 to go to the comparator circuitry 84.

As shown in FIG. 1, the device tester 30 is coupled to the device undertest (DUT) 31 through the parallel compare circuit 91. Therefore, in thepreferred embodiment, the DUT output signals on the leads 37-40 go firstto a parallel compare circuit 91. The multiple input single outputcomparator 84 is coupled to the device under test data leads forcomparing the device under test data output signals on the leads 37-40to each other and for producing the parallel compare circuit outputsignal on the lead 45.

Parallel compare circuit 91 takes all of the outputs 37-40 of a DUT 31and compares the outputs 37-40 with each other. During a read cycle, amultiple input single output comparator 84 such as the SN74F521available from Texas Instruments performs the comparison of the outputson data input/data output lines 37-40 of DUT 31. If the outputs 37-40are all of a similar voltage level which corresponds to the same logiclevel (logic 1 or logic 0) then the parallel compare circuit outputsignal is a first state. If the outputs 37-40 have different voltagelevels which correspond to different logic levels, then the parallelcompare circuit output signal is a second state.

Next, the comparator 84 compares the stored duplicated test data signalswith one another and produces a single parallel compare circuitry outputsignal on line 45 having a first state if all of the stored duplicatedtest data signals are at a similar voltage level corresponding to thesame logic level or a second state if at least one of the storedduplicated test data signals has a voltage corresponding to a differentlogic level as the others of the stored duplicated test data signals.

The transceiver circuit 41 next compares the parallel comparator circuitoutput signal on line 45 with the stored test data signal pattern in thestorage register 92 to produce a test result signal which is a passstate if the parallel comparator circuit output signal pattern matchesthe stored test data signal pattern or which is a fail state if theparallel comparator circuit output signal pattern is different than thestored test data signal pattern.

Since only one transceiver circuit 41 is needed to perform the devicetest for this four data input/output device under test 31, the threeremaining transceiver circuits 42-44 are available to concurrently testthree additional multiple data input/output devices 51, 61, and 71 vialeads 46, 47, and 48 and parallel comparator circuitry 96, 97, and 98.

Still other configurations could be comprehended by persons skilled inthe art. For instance the invention could be implemented on aperformance board, a load board or any other interface between the DUT31 and the device tester 30. Additionally, the invention can beadvantageously used to test other devices with multiple datainputs/outputs such as application specific integrated circuits.

While in accordance with the provisions and statutes there has beenpresented an illustrative embodiment of the invention, certain changesmay be made without departing from the spirit of the invention as setforth in the appended claims. Various modifications of the disclosedembodiment will become apparent to persons skilled in the art uponreference to the description of the invention. It is thereforecontemplated that the appended claims will cover any such modificationsor embodiments as fall within the true scope of the invention.

What is claimed is:
 1. A method for testing a semiconductor devicecomprising the steps of:a) sending an address signal from a devicetester to a device under test having plural storage locations; b)storing a test data signal in a register located in said device tester;c) sending said test data signal from said device tester to parallelcompare circuitry; d) duplicating said test data signal in said parallelcompare circuitry and storing said duplicated test data signals in saiddevice under test in plural storage locations selected by said addresssignal; e) re-addressing said plural storage locations having saidduplicated test data signals stored therein and reading out said storedduplicated test data signals from said plural storage locations to saidparallel compare circuitry in response to a read signal; f) comparingread out said stored duplicated test data signals with one another insaid parallel compare circuitry and producing a parallel comparecircuitry output signal having a first state if all of said storedduplicated test data signals are at a similar voltage levelcorresponding to a same logic level or a second state if at least one ofsaid stored duplicated test data signals has a voltage which correspondsto a different logic level as the others of said stored duplicated testdata signals; and g) sending said parallel compare circuitry outputsignal to said device tester.
 2. The method of claim 1 wherein saidduplicating step includes:duplicating said test data signal by enablingmultiple paths through said parallel compare circuitry in response to awrite signal; and storing said duplicated test data signals in saidplural storage locations in said device under test in response to saidwrite signal.
 3. The method of claim 2 wherein said comparing stepfurther includes:disabling said multiple paths through said parallelcompare circuitry in response to said read signal.
 4. The method ofclaim 1 further comprising the step of:comparing said parallelcomparator circuitry output signal with said stored register test datasignal to produce a test result signal which is a pass state if saidparallel comparator circuitry output signal matches said stored registertest data signal or which is a fail state if said parallel comparatorcircuitry output signal is different than said stored register test datasignal.
 5. A test system comprising:a socket for coupling to aparticular device under test, said socket having plural data leads, saidparticular device under test having plural data leads and plural storagelocations; a device tester coupled to said socket, said device testerincluding:a register, an address bus, control circuitry for sendingaddress signals from said device tester over the address bus to saidsocket and for storing data signals created by said control circuitry inthe register in said device tester, and transceiver circuitry coupled tosaid control circuitry for sending said created data signals via aparallel compare circuitry data lead from said device tester to aparallel compare circuitry; said test system further comprising: saidparallel compare circuitry coupled to said transceiver circuitry and tosaid plural data leads of said socket for sending said created datasignals from said transceiver circuit to said plural storage locationsin said device under test in response to address signals sent from thecontrol circuit, said parallel compare circuitry reading out stored datasignals from said plural storage locations in said device under testthrough said plural data leads of said socket and determining if one ofsaid read out stored data signals on said socket plural data leads isdifferent from other read out stored data signals on said socket pluraldata leads, then said parallel compare circuitry producing a parallelcompare output signal on said parallel compare data lead; and saidtransceiver circuitry comparing said data signal from said register withsaid parallel compare output signal and producing a pass signal if saidparallel compare output signal matches said register data signal, a failsignal if said register data signal is different than said parallelcompare output signal.
 6. The test system of claim 5 wherein saidparallel compare circuitry comprises:one or more gating transistorsresponsive to a control signal from said control circuitry for couplingsaid transceiving circuitry to said socket when data is sent to saidsocket, and for disabling a path between said socket and saidtransceiving circuitry when data is sent back from said socket to saidtransceiving circuitry; and a comparator coupled to said socket pluraldata leads for comparing said stored data signals on said socket pluraldata leads to each other, then said comparator producing said parallelcompare output signal on said parallel compare data lead responsive tosaid comparison.